Semiconductor circuit arrangement and a method for producing same

ABSTRACT

The invention relates to a semiconductor circuit arrangement having a circuit element that is embodied in a semiconductor substrate ( 1 ) of a first conductivity type in an integrated manner and is provided with at least one gate electrode (G 1 , G 2 ) and a first (D) and a second electrode (S). The first electrode connection (D) is configured by means of a connection tub that is embedded in the semiconductor substrate and pertains to a second conductivity type which is opposite the first conductivity type and a lower area of the connection tub, whereby said area is located in the connection tub, pertains to the second conductivity type and is higher doped in relation to the connection tub. The invention is characterised in that the lower area of the connection tub is embodied in the main surface of the semiconductor substrate, is allocated to the first electrode connection (D), pertains to the second conductivity type and ends in front of the tub area of the first conductivity type of the at least one gate electrode.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0001] The preferred embodiments described hereinbelow do not limit thescope of the claims.

[0002] The semiconductor circuit arrangement shown in FIG. 1 comprises ahigh-frequency MOS tetrode as a circuit element of an integratedsemiconductor circuit according to the particularly preferred exemplaryembodiment of the invention. It is produced according to a standard CMOSprocess method, which is assumed to be known, with a semiconductorsubstrate 1 made of p-conducting silicon (p-doping=first conductivitytype according to this definition), the circuit element which is formedin an integrated manner having at least two control terminals made ofpolysilicon 6 on gate dielectrics 12, namely a high-frequency gate G1with a channel region VT1 and a control gate G2—isolated by theintermediate region—with a channel region VT2, and also a firstelectrode terminal, namely a drain terminal D, and a second electrodeterminal, namely a source terminal S (comprising a source So and asubstrate terminal Su). The channel regions VT1 and VT2 arranged belowthe poly-gates G1 and G2 may be doped differently by different channelimplantations, that is to say also be, for instance, in each case n- orp-doped. A p-type region 2 formed in the substrate 1 by doping serves asa p-type well and the p+-type region embedded therein serves as asubstrate terminal. The reference numerals 3, 4 and 5 designate lightlydoped n-LDD regions (LDD=lightly doped drain) in each case in source,drain and intermediate regions. Spacers 7 made of a suitable dielectricare formed laterally beside the gates G1 and G2; the reference numerals8, 9 and 11 designate n+-doped contact regions in the source terminal S,drain terminal D, and also in the intermediate region between the twogates, the contact regions 8, 9 and 11 as can be seen in theillustration in each case from source S and intermediate region beingisolated by the spacer 7 from the relevant gate or channel. A largerdistance between the gate G2 or channel and the drain terminal D is setto a suitable setting by means of a mask. The gate terminals G1 and G2are partly or else completely implanted with n+-type doping. The p-typewell 2 ends in the region between the gate G2 and the n+-doped contactregion 11 of the drain terminal D. R designates a high-resistanceresistor.

[0003]FIG. 2 shows, in an enlarged partial view, further details on thedrain construction according to the invention, with which it waspossible to obtain an increase in the drain-well breakdown voltage. Theincreased terminal resistance due to this construction in comparisonwith the customary standard CMOS drain construction has no disadvantageswhatsoever in most applications, since the output of the tetrodes e.g.in tuners is connected at high resistance. In addition to the increaseddielectric strength, this drain construction also yields a low outputcapacitance C_(OSS) and thus performance gains. For this reason, thisdrain construction can also preferably be used in those tetrodes inwhich the dielectric strength of a standard drain construction issufficient but which are used in high-frequency applications. The drainconstruction according to the invention as illustrated in more detail inFIG. 2 is distinguished by the fact that the p-conducting well region 2of the second gate terminal G2 stops before the n⁺-doped contact region11 of the drain terminal D, which is embedded in the terminal region(n-doped LDD) 4 of the second conductivity type n, which terminal regionis formed in the main surface of the semiconductor substrate 1.

[0004] The method thus is further characterized in that thesemiconductor circuit arrangement is formed as a discrete component withat least two control terminals. The method of one example provides thatthe semiconductor circuit arrangement constitutes a high-frequencytransistor with at least two control terminals.

[0005] In the semiconductor circuit arrangement of a preferredembodiment, the semiconductor circuit arrangement is formed as adiscrete component with at least two control terminals. In oneembodiment, the semiconductor circuit arrangement constitutes ahigh-frequency transistor with at least two control terminals.

[0006] Although other modifications and changes may be suggested bythose skilled in the art, it is the intention of the inventors to embodywithin the patent warranted hereon all changes and modifications asreasonably and properly come within the scope of their contribution tothe art. between gate G2 or channel and drain terminal D is set by asuitable setting by means of a mask. The gate terminals G1 and G2 arepartly or else completely implanted with n+-type doping. The p-type well2 ends in the region between the gate G2 and the n+-doped contact region11 of the drain terminal D.

[0007] R designates a high-resistance resistor.

[0008]FIG. 2 shows, in an enlarged partial view, further details on thedrain construction according to the invention, with which it waspossible to obtain an increase in the drain-well breakdown voltage. Theincreased terminal resistance due to this construction in comparisonwith the customary standard CMOS drain construction has no disadvantageswhatsoever in most applications, since the output of the tetrodes e.g.in tuners is connected at high resistance. In addition to the increaseddielectric strength, this drain construction also yields a low outputcapacitance C_(OSS) and thus performance gains. For this reason, thisdrain construction can also preferably be used in those tetrodes inwhich the dielectric strength of a standard drain construction issufficient but which are used in high-frequency applications. The drainconstruction according to the invention as illustrated in more detail inFIG. 2 is distinguished by the fact that the p-conducting well region 2of the second gate terminal G2 stops before the n⁺-doped contact region11 of the drain terminal D, which is embedded in the terminal region(n-doped LDD) 4 of the second conductivity type n, which terminal regionis formed in the main surface of the semiconductor substrate 1.

[0009] List of Reference Symbols

[0010]1 Semiconductor substrate

[0011]2 p-type region

[0012]3, 4, 5 Lightly doped n-LDD regions

[0013]6 Polysilicon

[0014]7 Spacers

[0015]8, 9, 11 n+-doped contact regions

[0016]10 Silicide regions

[0017]12 Gate dielectric

[0018]13 Gate poly

[0019]14 TEOS-Si02 layer

[0020] G1 High-frequency gate

[0021] G2 Control gate

[0022] D Drain terminal

[0023] S Source terminal

[0024] VT1, VT2 Channel regions

1. A method for producing a semiconductor circuit arrangement having acircuit element which is formed in an integrated manner in asemiconductor substrate (1) of a first conductivity type and has atleast one control terminal (G1, G2) and a first (D) and second electrodeterminal (S), the first electrode terminal (D) being formed by aterminal well—embedded within a in the semiconductor substrate—of asecond, second conductivity type opposite to the first conductivity typeand a sub-well region of the second conductivity type which is situatedwithin the terminal well but is doped more highly than the terminalwell, characterized in that the sub-well region of the secondconductivity type which is formed in the main surface of thesemiconductor substrate and is assigned to the first electrode terminal(D) ends before the well region of the first conductivity type of the atleast one control terminal.
 2. The method as claimed in claim 1,characterized in that the semiconductor circuit arrangement is formed asa discrete component with at least two control terminals.
 3. The methodas claimed in claim 1 or 2, characterized in that the semiconductorcircuit arrangement constitutes a high-frequency transistor with atleast two control terminals.
 4. A semiconductor circuit arrangementhaving a circuit element which is formed in an integrated manner in asemiconductor substrate (1) of a first conductivity type and has atleast one control terminal (G1, G2) and a first (D) and second electrodeterminal (S), the first electrode terminal (D) being formed by aterminal well—embedded within a in the semiconductor substrate—of asecond, second conductivity type opposite to the first conductivity typeand a sub-well region of the second conductivity type which is situatedwithin the terminal well but is doped more highly than the terminalwell, characterized in that the sub-well region of the secondconductivity type which is formed in the main surface of thesemiconductor substrate and is assigned to the first electrode terminal(D) ends before the well region of the first conductivity type of the atleast one control terminal.
 5. The semiconductor circuit arrangement asclaimed in claim 4, characterized in that the semiconductor circuitarrangement is formed as a discrete component with at least two controlterminals.
 6. The semiconductor circuit arrangement as claimed in claim4 or 5, characterized in that the semiconductor circuit arrangementconstitutes a high-frequency transistor with at least two controlterminals.